1. Field of the Invention
The present invention is directed to a digital router/signal processor, and more particularly, to a multi-channel superconducting digital signal processing method for analog-to-digital signal conversion.
2. Discussion of the Related Art
Different modulation techniques are known in the art, such as amplitude modulation, frequency modulation, phase modulation, etc., that impress information onto a carrier signal to be transmitted. The carrier signal is received by a receiver that removes the carrier signal to separate and decipher the transmitted information. To remove the carrier signal, state of the art receivers typically include an analog mixer or a frequency downconverter that multiplies the received carrier signal with a local oscillator signal to convert the signal to a lower intermediate or baseband frequency. The downconverted frequency signal is then filtered by a bandpass filter that passes the frequencies of interest that include the extracted information. The filtered signal is then converted to a digital signal by an analog-to-digital (A/D) converter to provide a digital representation of the information that is subsequently processed by a microprocessor. This general description of the process for extracting information from a carrier signal is well known to those skilled in the art.
Existing superconducting technology can simultaneously perform frequency translation (up or down conversion), bandpass filtering, and analog-to-digital conversion on the analog signal at its input. Oscillator/counter A/D converters that use superconducting, Josephson single flux quantum (SFQ) circuits for converting an analog signal to a digital signal are known in the art. See, for example, L. R. Eaton, et al., xe2x80x9cDesign of a 10 K NbN A/D Converter for IR Focal Plane Array Sensors,xe2x80x9d IEEE Transactions on Applied Superconductivity, 5, 2457, (1995) and U.S. Pat. No. 5,942,997. An improvement to the oscillator/counter A/D converter architecture of the type disclosed in the L. R. Eaton et al. Article and U.S. Pat. No. 5,942,997 can be found in U.S. Pat. No. 6,127,960, which is hereby incorporated by reference.
A general depiction of a digital signal processor 10 of the type disclosed in U.S. Pat. No. 6,127,960 is shown in FIG. 1. An analog input signal 12 to be converted is applied to a bandpass filter 11. The filtered signal from the bandpass filter 11 is applied to a voltage control pulse generator (VCPG) 14 that generates pulses based on the applied voltage of the filtered signal. The frequency of an output pulse train 18 from the VCPG 14 is directly proportional to the input voltage level. The pulse train 18 is gated by a pulse gate (PG) 20, where the pulse gate width is determined by a gate Flo signal 22. The pulse train 18 is effectively mixed with the Flo signal 22 which is used to control the frequency translation process.
The pulses that pass through the pulse gate 20 get multiplied and accumulated in a multiply-accumulator circuit (MAC) 24. A general depiction of the MAC 24 is disclosed in U.S. Pat. No. 6,288,600, referenced above. The MAC 24 multiplies the series of pulses by a binary coefficient and accumulates the product for a predetermined period of time. The MAC 24 improves the frequency response and eliminates the periodic responses that are out of band, thus eliminating the direct current (DC) response. A digital control signal 25 is applied to the MAC 24 to program the bandpass filter response. The digital control signal 25 includes a reset signal that defines a predetermined sampling period and provides an initiation of a new accumulation of outputs from the pulse gates 20. The sampling period covers a plurality of consecutive control pulses of the Flo signal 22. The process converts the gated pulses into digital words 26. The output of the MAC 24 is the digital version of the analog signal at the VCPG""s input. This operation produces an analog-to-digital conversion of a non-integrating analog-to-digital converter.
A multi-channel approach could offer more operational flexibility in terms of functionality and scaleability. With a multi-channel approach the end user will have a greater flexibility in configuring and reconfiguring a radio frequency (RF) spectrum of interest to perform specific operational needs or to adapt to a changing input signal environment without having to implement new design/manufacturing cycles.
It is an object of the present invention to provide a multi-channel approach to digital signal processing in a single assembly that allows for greater end-user operational flexibility and is easily scaleable and configurable as compared to a single-channel approach. Such a multi-channel approach provides a significant cost saving.
In accordance with the teachings of the present invention, a multi-channel digital router/signal processor is disclosed that provides frequency translation, bandpass filtering, routing, wideband channelization, digital multiplexing, analog-to-digital interleaved sampling, and channel path redundancy functions. The present invention accomplishes the multi-channel approach by expanding on a single channel approach through the use of pulse splitters (PS), pulse gates (PG), and pulse combiners (PC), and multiplying and accumulating the RF spectrum input signal to obtain a channel routed/processed digital output signal. Accordingly, the present invention will enable the end user to have a greater operational flexibility in configuring specific operational needs without the sacrifices afforded to size, weight and DC power. Additional channels could be added by increasing the size of the pulse splitters and pulse combiners to provide scaleability. This approach would also have a significant cost saving regarding design/manufacturing cycles to meet system requirements.